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| interface my_if();
logic [7:0] some_data;
endinterface
module dut(my_if mif);
initial begin
$monitor($time," mif.some_data=%2x",
mif.some_data);
end
endmodule
class class_stimulus;
virtual my_if port_vif;
int my_aaa, my_bbb;
function new(input int aaa,bbb);
my_aaa = aaa;
my_bbb = bbb;
endfunction
task run_t(virtual my_if ports);
this.port_vif = ports;
repeat (1) begin
port_vif.some_data = my_aaa;
#2;
port_vif.some_data = my_bbb;
#2;
end
this.port_vif = null;
endtask
endclass
program test(my_if this_if);
initial begin
class_stimulus class_stimulus_u = new(.aaa(4), .bbb(7));
class_stimulus class_stimulus_u2 = new(.aaa(3), .bbb(9));
class_stimulus_u.run_t(this_if);
#33;
class_stimulus_u2.run_t(this_if);
#122;
$finish;
end
endprogram
module mem_tb();
my_if my_connection();
dut my_dut(.mif(my_connection));
test my_test(.this_if(my_connection));
endmodule
|