Static vs. Automatic storage
See 1800-2012.pdf SystemVerilog LRM Section 6.21 Scope and lifetime
.
The difference between automatic and static storage types is illustrated, by using delays between when storage is assigned (call to add_task) and when it used (the final display statement in add_task).
A task in a module is static, by default.
Static and Automatic are lifetime qualifiers, which indicate the default lifetime of their storage.
By changing the lifetime of the task add_task() from static to automatic, we see that the arguments passed into each call retain their value. i.e. there is no overwriting happening of the variables which store those arguments
Overwriting happens when the task has a static lifetime.
A static variable has its storage allocated when the variable is instantiated, and it is never removed/destroyed.
An automatic variable has its storage allocated when it is used and it is removed/destroyed when the accessing code is exited.
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| module top();
//ACTION: Change the task lifetime between static and automatic, below, and run the code.
//task static add_task(input int a, b); //A static task by default. Inputs are static, so only a single storage location for each value.
task automatic add_task(input int a, b); //An automatic task. Inputs are static, so only a single storage location for each value.
$display("time:%0t: add_task() called. a:%0d b:%0d",$time,a,b);
#2;
$display("time:%0t: The sum (%0d+%0d) is %0d",$time,a,b,a+b); //Then the values are added together.
endtask
initial begin
fork
begin : P1
add_task(100,50);
end
begin : P2
#1;
add_task(3,5);
end
join
end
endmodule
|
// This example is a modified version of example code supplied by user puttasatish
here:
// https://verificationacademy.com/forums/systemverilog/what-exact-difference-between-static-tasks/functions-and-automatic-tasks/functions-please-explain-clear-example
