18 static vs. automatic storage - part 1

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// Static vs. Automatic storage
//
// In Verilog 1995, storage was static.  So, a variable in functions or tasks would exist in a single space in memory, and exist throughout a simulation.
//
// Since Verilog 2001, we can use the 'automatic' keyword (so the stack is used for local variables).  Now, variables can be unique for each scope.  
//   See 1800-2012.pdf SystemVerilog LRM  Section 6.21 "Scope and lifetime".
//
module top;
  static int module_int;  // by default is static

  class my_class;
    static int class_int;  //automatic by default
  endclass

  my_class class1, class2;

  initial begin
    class1=new();
    class2=new();
    $display("module_int:%0d",module_int);
    $display("my_class::class_int:%0d",my_class::class_int);

    my_class::class_int = 12;
    $display("my_class::class_int:%0d  class1.class_int:%0d  class2.class_int:%0d",my_class::class_int, class1.class_int, class2.class_int);
    class1.class_int = 14;
    $display("my_class::class_int:%0d  class1.class_int:%0d  class2.class_int:%0d",my_class::class_int, class1.class_int, class2.class_int);
    class2.class_int = 16;
    $display("my_class::class_int:%0d  class1.class_int:%0d  class2.class_int:%0d",my_class::class_int, class1.class_int, class2.class_int);

    $display("",);
  end
endmodule